ISE WEB PACK - rychlost, licence
Jaroslav Buchta
jaroslav.buchta na hascomp.cz
Sobota Duben 13 11:36:30 CEST 2013
Jo aha, to jsem zapomel, ze jsem musel doplnit ty nabizene options do
ucf souboru...
Cili zacatek pak vypada takto:
# clock pin for Nexys 2 Board
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "instClkDllDiv16/CLKDLL_inst/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE =
FALSE;
NET "clk" LOC= "B8"; # Bank = 0 , Pin name = IP_L13P_0/GCLK8 , Type =
GCLK , Sch name = GCLK0
# NET "clk1" LOC= "U9"; # Bank = 2 , Pin name = IO_L13P_2/D4/GCLK14 ,
Type = DUAL/GCLK , Sch name = GCLK1
.............
NET "UsbClk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "UsbClk" LOC= "T15"; # Bank = 2 , Pin name = IO/VREF_2 , Type =
VREF , Sch name = U-IFCLK
................
Dne 13.4.2013 11:30, Draček Fráček napsal(a):
> Tak me to na ISE 14.5 po te co migruji ze stareho ISE projektu a
> zpustim preklad za 1,5min zahlasi pri place route chybu
>
> Place:1018 - A clock IOB / clock component pair have been found that
> are not placed at an optimal clock IOB / clock site pair. The clock
> component <UsbClk_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y0>. The IO
> component <UsbClk> is placed at site <T15>. This will not allow the
> use of the fast path between the IO and the Clock buffer. If this sub
> optimal condition is acceptable for this design, you may use the
> CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this
> message to a WARNING and allow your design to continue. However, the
> use of this override is highly discouraged as it may lead to very poor
> timing results. It is recommended that this error condition be
> corrected in the design. A list of all the COMP.PINs used in this
> clock placement rule is listed below. These examples can be used
> directly in the .ucf file to override this clock rule.
> < NET "UsbClk" CLOCK_DEDICATED_ROUTE = FALSE; >
> a
> Place:1012 - A clock IOB / DCM component pair have been found that are
> not placed at an optimal clock IOB / DCM site pair. The clock
> component <instClkDllDiv16/CLKDLL_inst/DCM_SP> is placed at site
> <DCM_X2Y3>. The clock IO/DCM site can be paired if they are
> placed/locked in the same quadrant. The IO component <clk> is placed
> at site <IPAD39>. This will not allow the use of the fast path
> between the IO and the Clock buffer. If this sub optimal condition is
> acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE
> constraint in the .ucf file to demote this message to a WARNING and
> allow your design to continue. However, the use of this override is
> highly discouraged as it may lead to very poor timing results. It is
> recommended that this error condition be corrected in the ...
> NOTE: This message is very long (~1 K) and has been shortened to a
> maximum of 1000 characters for viewing in this context.
> Please refer to the corresponding ASCII report for the full
> message.
>
>
>
> Dne 13. dubna 2013 8:40 Jaroslav Buchta <jaroslav.buchta na hascomp.cz
> <mailto:jaroslav.buchta na hascomp.cz>> napsal(a):
>
> Tak jestli to nekdo muzete zkusit, abych si udelal predstavu - je
> to tento projekt
> http://www.digilentinc.com/Data/Products/NEXYS2/Nexys%202%201200K%20BIST.zip
> odsud
> http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2 (Nexys2
> Board verification Project - (for 1200K boards))
>
> Neda se nejak snizi optimalizace a zvysit rychlost, pokud neni
> FPGA prilis vyuzito?
>
>
>
> Dne 13.4.2013 10:04, Draček Fráček napsal(a):
>> ISE 14,5, na i7 920, Win 7 64bit
>> File, Open Example, XAPP 217: Gold Code Generator
>> kompletni preklad cca 35s ted odszkouseno
>>
>> Na mem vykopavkovem notebooku nejake Intel jedno jadro, 2GB RAM,
>> Win7
>> 32bit, to bude trvat dele, ale odhaduji tak kolem 1 minuty. Vecer
>> mohu vyzkouset.
>> Pripadne nekam hodte vas kod (projekt) a ja to zkusim prelozit na
>> obojim.
>>
>> Martin
>>
>>
>>
>> Dne 13. dubna 2013 7:54 Jaroslav Buchta
>> <jaroslav.buchta na hascomp.cz <mailto:jaroslav.buchta na hascomp.cz>>
>> napsal(a):
>>
>> - je normalni, ze je to ukrutne pomale? Na i5-2450 a 4GB
>> pameti je synteza otazkou mnoha minut, spis pres 10 po kazde
>> i minimalni zmene designu (vzorova aplikace pro nexys 2 ale
>> trivialni dekoder taky trval minuty)
>> Je to dan za free verzi nebo to takhle funguje normalne?
>> Pokud bych na to kupoval nove pocitadlo, co je dulezite?
>> Procesor s hodne jadry, rychly disk (pripadne SSD) a hodne
>> pameti? Grafika predpokladam ne...
>> - free licence na jednu registraci se da poridit jen na jeden
>> pocitac? Z upozorneni kdyz jsem to menil se mi zdalo, ze je
>> pocet preneseni dokonce nejak omezen na 3... Jak to je?
>> - na Win8 aktualni verze 14.5 nefunguje...
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