stm32 registro trapeni

[Jan Waclawek]

Este aby som to trocha viac obkecal.

Ten I2C v 'G4 (ako aj takmer vsetky ostatne moduly v takmer vsetkych STM32
novsich ako cojaviem 5 rokov) maju dve casovacie domeny: pristup k
registrom ma hodiny APBCLK z APB zbernice na ktorom je dany modul
zaveseny, ale zvysok toho I2C stroja bezi z tzv. "kernel" hodin, ktore su
v konkretnom pripade 'G4 volitelne v RCC medzi SYSCLK/HSI/APB. 

To znamena, ze medzi registrami a celym zvyskom toho I2C modulu su
synchronizatory, inaksie povedane, zapis do registrov sa neobjavi okamzite
v skutocnom pracovnom jadre toho modulu. U toho I2C modulu je to vidiet na
blokovom diagrame na zaciatku kapitoly, ale aj v tom, ze niektore registre
maju tuto poznamku:

Access: No wait states, except if a write access occurs while a write
access to this register is
ongoing. In this case, wait states are inserted in the second write access
until the previous
one is completed. The latency of the second write access can be up to
2 x PCLK1 + 6 x I2CCLK.

pricom nie je jasne, co sa stane, ak sa rychlo za sebou zapise do dvoch
roznych registrov s touto poznamkou.

Z toho potom vyplyvaju prave rozne tie obvykle zle alebo vobec
nedokumentovane podmienky ze "nemoze sa zapisat nieco prilis rychlo alebo
v tomto a tomto poradi", rozne komplikovane erraty(*); no a tiez to, ze
nejaky kod autorovi kniznice je "mne to funguje" ale pri pouziti "lepsej"
optimalizacie prestane fungovat,  atd.atd.

wek


(*) Napr.
If the first of the two bytes is written in the I2C_TXDR
register in less than two I2C kernel clock cycles after the TXIS/DMA
request, and the ratio between APB clock
and I2C kernel clock frequencies is between 1.5 and 3, the second byte
written in the I2C_TXDR is not internally
detected. This causes a state in which the I2C peripheral is stalled [...]