VHDL to Verilog

[Jindroush]

A vy chcete 'and' nebo '&'?

On 18.04.2021 18:21, Jaroslav Buchta wrote:
> Tak se ucim VHDL, to musel vymyslet silenec ;-)
> Jedna vetsi nez normalni zahada...
>
> Mam signaly:
>
> binout                : OUT std_logic_vector(7 downto 0));
>
> SIGNAL citac : std_logic_vector(3 downto 0);
> TYPE states IS (S0, S1, S2, S3);
> SIGNAL state : states := S0;
>
> signal led1 : BIT;
>
> konstrukce
> binout <= citac & conv_std_logic_vector(states'pos(state), 3) & led1;
> hodi chybu
> Error (10327): VHDL error at xxxx.vhd(200): can't determine definition 
> of operator ""&"" -- found 0 possible definitions
>
> po zmene
> binout <= citac & conv_std_logic_vector(states'pos(state), 3) & "1";
> probehne analyza i synteza OK.
>
> Blbe neco vidim, nebo v cem muze byt problem? uz zkousim vsechno mozne 
> asi hodinu, ty slozitejsi konverze asi problem nedelaji kdyz to jde s 
> konstantnim bitem??? 

-- 
Jindroush <jindroush at seznam.cz>