Asi trapna chyba - verilog HDL

[Jaroslav Buchta]

Narazil jsem na zahadu ktera je predpokladam zpusobena jen tim, ze mi 
neco nedochazi... Mam cast designu, kde inicializuji cas pameti a 
registr, je to jen pro ucely ladeni, tato cast je na konci textu vypsana.

Hacek je v
         ldcntr <= ldcntr == 4'd15 ? ldcntr : ldcntr + 4'd1;    // takto 
to nefunguje, projde to jen nektere stavy (asi 1/3) a celkove to v 
simulaci nefunguje



Pokud je
         ldcntr <= ldcntr == 4'd14 ? ldcntr : ldcntr + 4'd1;    // nebo 
13,  takto to funguje, projde vsechny stavy v simulaci  dle ocekavani...



Ma nekdo nejaky napad, v cem je chyba?
Chapu, ze to syntezator optimalizuje a muze nefunkcni stavy vyhazet, ale 
jednak tady jsou funkcni i ty prodlevy a hlavne proc to se 14 funguje a 
s 15 ne, co jsem sakra prehlidnul?
-------------------------- Vypis inicializace 
--------------------------------

reg [3:0] ldcntr;
reg [7:0] regDevSel;
reg [4:0] regRegSel;
reg [31:0] regDo32;
reg regDw32;

assign devSelect = regDevSel;
assign devRegSel = regRegSel;
assign do32 = regDo32;

always @(posedge clk)
begin
     ldcntr <= ldcntr == 4'd15 ? ldcntr : ldcntr + 4'd1;
     dw32 <= 1'b0;
     case (ldcntr)
         1: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd0;
             regDo32 <= 32'h80000000;
             dw32 <= 1'b1;
         end
         2:;
         3:;
         4: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd16;
             regDo32 <= 32'hfff00010;        // steps, speed [19:8]
             dw32 <= 1'b1;
         end
         5: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd17;
             regDo32 <= 32'h00030003;        // acc, dec steps
             dw32 <= 1'b1;
         end
         6: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd18;
             regDo32 <= 32'h0000000;            // M1,accl
             dw32 <= 1'b1;
         end
         7: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd19;
             regDo32 <= 32'h01000000;        // M2, acch
             dw32 <= 1'b1;
         end
         8: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd20;
             regDo32 <= 32'h00000000;        // M3, decl
             dw32 <= 1'b1;
         end
         9: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd21;
             regDo32 <= 32'h03000000;        // M4, dech
             dw32 <= 1'b1;
         end
         10: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd22;
             regDo32 <= 32'h3f000000;        // M5, speed [25:20]
             dw32 <= 1'b1;
         end
         11: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd23;
             regDo32 <= 32'h1f000000;        // M6, speed [31:26]
             dw32 <= 1'b1;
         end
         12: begin
             regDevSel <= 8'b00000001;
             regRegSel <= 5'd0;
             regDo32 <= 32'h01000000;        // start
             dw32 <= 1'b1;
         end


     endcase




end



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