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Narazil jsem na zahadu ktera je predpokladam zpusobena jen tim, ze
mi neco nedochazi... Mam cast designu, kde inicializuji cas pameti a
registr, je to jen pro ucely ladeni, tato cast je na konci textu
vypsana.<br>
<br>
Hacek je v <br>
ldcntr <= ldcntr == 4'd15 ? ldcntr : ldcntr + 4'd1; //
takto to nefunguje, projde to jen nektere stavy (asi 1/3) a celkove
to v simulaci nefunguje<br>
<br>
<img src="cid:part1.09090008.05020501@hascomp.cz" alt=""><br>
<br>
Pokud je <br>
ldcntr <= ldcntr == 4'd14 ? ldcntr : ldcntr + 4'd1; //
nebo 13, takto to funguje, projde vsechny stavy v simulaci dle
ocekavani...<br>
<br>
<img src="cid:part2.08060500.07070803@hascomp.cz" alt=""><br>
<br>
Ma nekdo nejaky napad, v cem je chyba?<br>
Chapu, ze to syntezator optimalizuje a muze nefunkcni stavy vyhazet,
ale jednak tady jsou funkcni i ty prodlevy a hlavne proc to se 14
funguje a s 15 ne, co jsem sakra prehlidnul?<br>
-------------------------- Vypis inicializace
--------------------------------<br>
<br>
reg [3:0] ldcntr;<br>
reg [7:0] regDevSel;<br>
reg [4:0] regRegSel;<br>
reg [31:0] regDo32;<br>
reg regDw32;<br>
<br>
assign devSelect = regDevSel;<br>
assign devRegSel = regRegSel;<br>
assign do32 = regDo32;<br>
<br>
always @(posedge clk)<br>
begin<br>
ldcntr <= ldcntr == 4'd15 ? ldcntr : ldcntr + 4'd1;<br>
dw32 <= 1'b0;<br>
case (ldcntr)<br>
1: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd0;<br>
regDo32 <= 32'h80000000;<br>
dw32 <= 1'b1;<br>
end <br>
2:;<br>
3:;<br>
4: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd16;<br>
regDo32 <= 32'hfff00010; // steps, speed
[19:8]<br>
dw32 <= 1'b1;<br>
end<br>
5: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd17;<br>
regDo32 <= 32'h00030003; // acc, dec steps<br>
dw32 <= 1'b1;<br>
end<br>
6: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd18;<br>
regDo32 <= 32'h0000000; // M1,accl<br>
dw32 <= 1'b1;<br>
end<br>
7: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd19;<br>
regDo32 <= 32'h01000000; // M2, acch<br>
dw32 <= 1'b1;<br>
end<br>
8: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd20;<br>
regDo32 <= 32'h00000000; // M3, decl<br>
dw32 <= 1'b1;<br>
end<br>
9: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd21;<br>
regDo32 <= 32'h03000000; // M4, dech<br>
dw32 <= 1'b1;<br>
end<br>
10: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd22;<br>
regDo32 <= 32'h3f000000; // M5, speed [25:20]<br>
dw32 <= 1'b1;<br>
end<br>
11: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd23;<br>
regDo32 <= 32'h1f000000; // M6, speed [31:26]<br>
dw32 <= 1'b1;<br>
end<br>
12: begin<br>
regDevSel <= 8'b00000001;<br>
regRegSel <= 5'd0;<br>
regDo32 <= 32'h01000000; // start<br>
dw32 <= 1'b1;<br>
end <br>
<br>
<br>
endcase<br>
<br>
<br>
<br>
<br>
end<br>
<br>
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