FPGA OpenRISC (bylo Verilog a FPGA (bylo FPGA Altera a NIOS))

Jaroslav Buchta jaroslav.buchta na hascomp.cz
Sobota Únor 14 20:19:39 CET 2015


Tak jsem zase mel chvili cas a chut na hrani, procesor zda se funguje,  
zatim jsem nabastlil jako instrukcni pamet pevny kod a jako datovou 
registr co se prenasi na 8 ledek.
Co je problem, nefunguje debugger - ne, ze by nefungoval vubec, ale dela 
uplne blbosti - pouzivam ted extra JTAG piny, na tom FT2232 a OpenOCD 
0.8.0 Vcera jsem zkousel interni Altera JTAG a fungovalo to o chlup lip 
nez naprimo ale taky blbe.
Resp. spolehlive slo treba mww do registru primo na WB sbernici ktery se 
prenasel na ledky, naprimo to jde nespolehlive, obcas se prenese chybny 
obsah, obcas nic.
Operace s procesorem - reset, halt... - sporadicka funkce, stale pise 
chyby CRC, kdyz uz se povedlo procesor zastavit, nacteny obsah registru 
byl dost spatny, treba sedelo 10b z 32, takze se neda rict, ze by to 
nefungovalo vubec ale je to nepouzitelne.
Zkousel jsem vsechno mozne, jde samozrejme o prevzate zdrojaky. TAP ID 
to cte spolehlive, na dratech by problem byt nemel, snizil jsem 
frekvenci JTAG na 300kHz a s jinymi procesory to stejne zapojene funguje.

Kdyz ucesu a poslu TOP verilog  nebo cely projekt, posoudi nekdo, jestli 
nemam neco uplne spatne propojene?
Zajima mne hlavne, jestli neni spis chyba na strane OpenOCD, provozuji 
to ve windows, tak jestli by pomohl prechod na linux, kde to podle 
nalezenych prispevku funguje dobre?

Jinak je to uzasne, uz jsem si asi 20 let nezaprogramoval v binarnim 
assembleru, nejak takto ;-) Planuju pridat uart a udelat aspon hello 
world ;-)
(pro zajimavost, s I-Cache to funguje tento kod o nekolik desitek % 
rychleji takto v interni pameti, u externi pameti to bude asi dost 
vyznamne  ale synteza sezere 2x tolik bloku (asi 4500 misto 2200, mam 
jich jen 6700) ...)

module OR1K_startup
   (
     input [6:2]       wb_adr_i,
     input           wb_stb_i,
     input           wb_cyc_i,
     output reg [31:0] wb_dat_o,
     output reg           wb_ack_o,
     input           wb_clk,
     input           wb_rst
    );

    always @ (posedge wb_clk or posedge wb_rst)
      if (wb_rst)
        wb_dat_o <= 32'h15000000;     //NOP
      else
        case (wb_adr_i)
       0 : wb_dat_o <= 32'h18000000;    //l.movhi r0, 0     
000110DDDDD----0KKKKKKKKKKKKKKKK
       1 : wb_dat_o <= 32'h18200000;    //l.movhi r1, 0     
000110DDDDD----0KKKKKKKKKKKKKKKK
       2 : wb_dat_o <= 32'h9c210001;    //l.addi r1, r1, 1 
100111DDDDDAAAAAIIIIIIIIIIIIIIII
       3 : wb_dat_o <= 32'hd4000800;    //l.sw r0+0, r1 110101II 
IIIAAAAA BBBBBIII IIIIIIII
       4 : wb_dat_o <= 32'h03fffffe;    //l.j -2         
000000NNNNNNNNNNNNNNNNNNNNNNNNNN
       5 : wb_dat_o <= 32'h15000006;
       6 : wb_dat_o <= 32'h15000007;
       7 : wb_dat_o <= 32'h15000008;
       8 : wb_dat_o <= 32'h15000009;
       9 : wb_dat_o <= 32'h1500000a;
      10 : wb_dat_o <= 32'h1500000b;
      11 : wb_dat_o <= 32'h1500000c;
      12 : wb_dat_o <= 32'h1500000d;
      13 : wb_dat_o <= 32'h1500000e;
      14 : wb_dat_o <= 32'h1500000f;
      15 : wb_dat_o <= 32'h15000010;
      16 : wb_dat_o <= 32'h15000011;
      17 : wb_dat_o <= 32'h15000012;
      18 : wb_dat_o <= 32'h15000013;
      19 : wb_dat_o <= 32'h15000014;
      20 : wb_dat_o <= 32'h15000015;
      21 : wb_dat_o <= 32'h15000016;
      22 : wb_dat_o <= 32'h15000017;
      23 : wb_dat_o <= 32'h15000018;
      24 : wb_dat_o <= 32'h15000019;
      25 : wb_dat_o <= 32'h1500001a;
      26 : wb_dat_o <= 32'h1500001b;
      27 : wb_dat_o <= 32'h1500001c;
      28 : wb_dat_o <= 32'h1500001d;
      29 : wb_dat_o <= 32'h1500001e;
      30 : wb_dat_o <= 32'h1500001f;
      31 : wb_dat_o <= 32'h15000020;
        endcase

    always @ (posedge wb_clk or posedge wb_rst)
      if (wb_rst)
        wb_ack_o <= 1'b0;
      else
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;

endmodule // OR1K_startup

module OR1K_dat
   (
     input [6:2]       wb_adr_i,
     input           wb_stb_i,
     input           wb_cyc_i,
     output reg [31:0] wb_dat_o,
     input [31:0]  wb_dat_i,
     output reg    wb_ack_o,
     input           wb_clk,
     input           wb_rst,
     input           wb_we,
      output [31:0]    data_o
    );

     reg [31:0] data;

     assign data_o = data;

    always @ (posedge wb_clk or posedge wb_rst)
      if (wb_rst)
         begin
             wb_dat_o <= 32'h00000000;
             data <= 32'h00000000;
         end
      else
        begin
            if (wb_stb_i & wb_cyc_i & wb_we)
                data <= wb_dat_i;
             else
                 wb_dat_o <= data;
         end


    always @ (posedge wb_clk or posedge wb_rst)
      if (wb_rst)
        wb_ack_o <= 1'b0;
      else
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;

endmodule // OR1K_dat


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