Xilinx VHDL?

[Petr Tošovský]

Coz neni synchronni design jak bylo pozadovano.

Tosa


Jan Smrz wrote:
> Mel jsem spatne nazvy hodin (clock a clk), tak jeste jednou.
>
>
> signal clock_en: std_logic;
> signal clock: std_logic;
> signal clock_out: std_logic;
>
>
> process (clock, rst)
> begin
>    if (rst = '1') then
>       clock_en <= '0';
>    elsif falling_edge(clock) then    -- prepiname v neaktivni 
> fazi                          -- hodin (kvuli zakmitum!)
>       clock_en <= not(clock_en);    -- delic 2
>    end if;
> end;
>
> -- clock enable
> clock_out <= clock and clock_en;
>
>
> J.S.
>
>