Fw: simulacia v ise7.1

[juraj michalek]

Diky Moc aj p. Tosovskemu

S pozdravom Juraj Michálek
www.toolsquare.com
----- Original Message ----- 
From: ""Ing. Zbyněk HEJDA"" <zbynek_hejda@rametchm.cz>
To: <michalek@toolsquare.com>; <hw-list@list.hw.cz>
Sent: Wednesday, February 22, 2006 12:31 PM
Subject: simulacia v ise7.1


> Dobry den,
> v priloze posilam test soubor pro otestovani citace. Pro vitvoreni
> vstupniho "clk" je dulezita rutina s navestim "tb".
>
> tb : PROCESS
>     BEGIN
>        for i in 0 to 100 loop
>          CLK <= '1';
>          wait for 5 ns; --doba trvani stavu H
>          CLK <= '0';
>          wait for 5 ns; -- doba trvani stavu L
>      end loop;
>   end process;
>
> -- 
> Electrical designer
> Ing. Zbynek Hejda
> RAMET C.H.M. a.s.
> Letecka 1110
> 686 04 Kunovice
> Czech Republik
> tel: +420572415281
> e-mail: zbynek_hejda@rametchm.cz
> www: www.rametchm.cz
>
>
>
> __________ Informacia od NOD32 1.1415 (20060221) __________
>
> Tato sprava bola preverena antivirusovym systemom NOD32.
> http://www.eset.sk
>
>


--------------------------------------------------------------------------------


>
> --------------------------------------------------------------------------------
> -- Company:
> -- Engineer:
> --
> -- Create Date:   13:40:07 09/06/2005
> -- Design Name:   main
> -- Module Name:   test.vhd
> -- Project Name:  citac
> -- Target Device:
> -- Tool versions:
> -- Description:
> -- 
> -- VHDL Test Bench Created by ISE for module: main
> --
> -- Dependencies:
> -- 
> -- Revision:
> -- Revision 0.01 - File Created
> -- Additional Comments:
> --
> -- Notes:
> -- This testbench has been automatically generated using types std_logic 
> and
> -- std_logic_vector for the ports of the unit under test.  Xilinx 
> recommends
> -- that these types always be used for the top-level I/O of a design in 
> order
> -- to guarantee that the testbench will bind correctly to the 
> post-implementation
> -- simulation model.
> --------------------------------------------------------------------------------
> LIBRARY ieee;
> USE ieee.std_logic_1164.ALL;
> USE ieee.std_logic_unsigned.all;
> USE ieee.numeric_std.ALL;
>
> ENTITY test_vhd IS
> END test_vhd;
>
> ARCHITECTURE behavior OF test_vhd IS
>
> -- Component Declaration for the Unit Under Test (UUT)
> COMPONENT main
> PORT(
> clk : IN std_logic;
> qa : out std_logic;
> q : OUT std_logic_vector(7 downto 0)
> );
> END COMPONENT;
>
> --Inputs
> SIGNAL clk :  std_logic := '0';
>
> --Outputs
> signal qa : std_logic;
> SIGNAL q :  std_logic_vector(7 downto 0);
>
> BEGIN
>
> -- Instantiate the Unit Under Test (UUT)
> uut: main PORT MAP(
> clk => clk,
> qa => qa,
> q => q
> );
>
> tb : PROCESS
> BEGIN
> for i in 0 to 100 loop
> CLK <= '1';
> wait for 5 ns;
> CLK <= '0';
> wait for 5 ns;
> end loop;
>   end process;
>
> END;
>
>
> __________ Informacia od NOD32 1.1415 (20060221) __________
>
> Tato sprava bola preverena antivirusovym systemom NOD32.
> http://www.eset.sk
>
>