CPLD syntax

[Michal HW]

Diky vsem za info, jsou to prvni pokusy dle Xilinx navodu. 
Zatim se snazim vubuc neco zkompilovat.
Michal

----- Original Message ----- 
From: "Jan Smrz" <jan.smrz@htc.honeywell.cz>
To: "HW-news" <hw-list@list.hw.cz>
Sent: Wednesday, July 20, 2005 3:30 PM
Subject: Re: CPLD syntax


Signal count_out musi byt tez typu std_logic_vector (0 to 3).
Jinak doporucuji spise pouzivat (3 downto 0).

J.S.


Michal HW wrote:
> Zkousim neco kompilovat s CPLD dle navodu:
>  
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>  
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>  
> entity prvni is
>     Port ( CLOCK : in std_logic;
>            DIRECTION : in std_logic;
>            COUNT_OUT : out std_logic);
> end prvni;
>  
> architecture Behavioral of prvni is
> signal count_int : std_logic_vector(0 to 3) := "0000";
> begin
> process (clock)
> begin
>    if CLOCK='1' and clock'event then
>       if DIRECTION='1' then  
>          count_int <= count_int + 1;
>       else
>          count_int <= count_int - 1;
>       end if;
>    end if;
> end process;
> COUNT_OUT <= count_int;
> end Behavioral;
>  
> Haze to chybu:
> ERROR:HDLParsers:800 - "C:/A/xilinx/projekty/prvni.vhd" Line 49. Type of 
> COUNT_OUT is incompatible with type of count_int.
> Co stim? Je to podle navodu, jen misto Spartana jsem tam dal 9500XC. 
> Spartan nebyl v nabidce.
>  
> Michal Gregor
>  
>
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