VHDL - edge sensitive problem

[Zdenek Aster]

Problem je v tom ze signalu test_sign, jste v podstate udelal hodiny
a jakmile neni na pinu, ktery lze rozvest tak mate smulu, takze bud
to to udelate synchrone a ted me nenapada jak to udelat na
hranu asynchrone. slo by treba kopirovat ten signal.


process (test_sig,clock)
signal test_old: std_logic;
begin
   if (test_clock'event and clock='1') then
     test_old = test_sig;
     if (test_old = '0' and test_sig='1')   then
      test<='0';
     else 
      test<='1';
     end if;
   end if;
end process;


----- Original Message ----- 
From: "Jiri Beranek" <beranek@gost-elektronic.cz>
To: <hw-list@list.hw.cz>
Sent: Tuesday, July 12, 2005 4:09 AM
Subject: VHDL - edge sensitive problem


Zdravim, mam problem s timto:


process (test_sig)
begin
 if (test_sig'event and test_sig='1')
  then
 test<='0';
 end if;
end process;

test_sig je vstup namapovany na pin SPARTANA II, ktery neni GCK.
Hlasi mi to nasledujici chybu:


Illegal LOC on IPAD symbol "test_sig" or BUFGP symbol

test_sig_BUFGP" (output signal=test_sig_BUFGP), IPAD-IBUFG should only be
LOCed

to GCLKIOB site.



Kdyz test_sig namapuju na pin ktery je GCK, tak je to OK.

Otazka je: co mam napsat  nebo udelat, aby to chodilo i s ne GCK piny?



Dekuji Jirka B.



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