VHDL - obousmerna sbernice
Petr Sremr
petr.sremr@hwserver.cz
Pondělí Duben 24 12:57:37 CEST 2006
Zdravim,
> Doporucujem vo vnutri pracovat s 2 nezavilymi zbernicami,
> vstupna - rozvedie vstupne data do reg. /zapisovat WR najlepsie synchronne
> ak sa da/
> vystupna - vpodstate mux. na zaklade adresy
>
> Obe zbernice spojit na pine pomocou vlozenych komponentov
> IBUF - pre vstupnu
> OBUFT /OBUFE/ - pre vystupnu trojstavovu, na tomto mieste priamo riadit 3
> stav /signalom RD&CS/
Tak jsem to nejak takto zkusil. Ty komponenty jsou super.
Tady je muj pokus pro jednobitovy pripad. Prosim, muzete se podivat, kde
delam chyby. S VHDL zacinam, a zrejme mi porad unikaji zakladni
principy. Mimo jine, dostavam tyto upozrneni:
WARNING:Xst:766 - D:/Projects/Logic_01/jspp/jspp1/jspp1.vhd (Line 56).
Generating a Black Box for component <obufe>.
WARNING:Xst:766 - D:/Projects/Logic_01/jspp/jspp1/jspp1.vhd (Line 60).
Generating a Black Box for component <ibuf>.
WARNING:Xst:819 - D:/Projects/Logic_01/jspp/jspp1/jspp1.vhd (Line 64).
The following signals are missing in the process sens
itivity list: rw.
------------------------------------------------------------------------
--
-- Zapis: Cteni:
-- | |
-- |-\________/-- |-------------
-- RW |=============> RW |=============>
-- | |
-- |----\___/---- |----\___/----
-- E |=============> E |=============>
-- | |
-- |xxxWWWxxxxxxx |xxxxxWWWxxxxx
-- Dx |=============> Dx |=============>
--
-- po celou dobu je
-- na sbernici 3.stav
--
-- x ... lib. data x ... 3.stav
-- W ... platna data W ... platna data
-- (strobovana sest. (sbernice aktivni)
-- hranou)
--
------------------------------------------------------------------------
-- http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0318_302.html
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jednoduchy_obvod is
Port (D: inout STD_LOGIC;
RW: in STD_LOGIC;
E: in STD_LOGIC);
end jednoduchy_obvod;
architecture moje_architektura of jednoduchy_obvod is
component OBUFE
port (O : out STD_LOGIC;
E : in STD_LOGIC;
I : in STD_LOGIC);
end component;
component IBUF
port (O : out STD_LOGIC;
I : in STD_LOGIC);
end component;
signal r: STD_LOGIC; -- registr, ktery. ctu/zapisuju
signal en: STD_LOGIC;
signal i: STD_LOGIC;
begin
output : OBUFE
port map (O => D,
E => en,
I => r);
input : IBUF
port map (O => i,
I => D);
pr_1: process (E)
begin
if (E'event and E = '0') then
if (RW = '0') then
r <= i;
end if;
end if;
en <= RW and not E;
end process;
end moje_architektura;
--
Petr Sremr
HW group
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