VHDL - obousmerna sbernice

[Pavel Prochazka.zde.cz]

zde je kus meho kodu:

*entity* transport1 *is*
 *Port* (DIR: in std_logic;
       A : buffer std_logic_vector(7 downto 0);
       B : buffer std_logic_vector(7 downto 0));
*end* transport1;

*architecture* behavioral *of* transport1 *is*
*begin*

 *process* (DIR) *begin*
 -- Signál DIR určuje tok dat.
  *if* DIR = '0' *THEN* A <= B;
   *else* A <= "ZZZZZZZZ"; *end if*;

  *if* DIR = '1' *THEN* B <= A;
  *else* B <= "ZZZZZZZZ"; *end if*;

 *end process*;
*end* behavioral;


kod muzete najit na:   http://prochazka.d2.cz/priklady1.php#29

Pavel prochazka.zde.cz



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