VHDL to Verilog

[balu]

obidva jazyky su rovnocenne. Treba ale vediet co robit :-)

Kod sa musi pisat podla funkcie, nie podla toho ako by som to zadratoval 
s integrovanymi obvodmi a to potom zapisal vo VHDL. To je zakladny a 
najvacsi problem pre zaciatocnikov. Prestat rozmyslat v integrovanych 
obvodoch a dratoch, to nie je dobre. Inak nie je zvladnutie obidvoch 
nijak zlozite.

b.



On 19/04/2021 08:20, Jaroslav Buchta wrote:
> Dik za info, asi nejrozumnejsi reseni bude nahradit vsude typ bit za 
> std_logic, to jede dle predpokladu
> Ale jak zkonvertovat bit na std_logic, na to jsem teda neprisel, 
> To_Std_Logic nejde std_logic(led1) hodi chybu, ze nelze zkonvertovat 
> nit na std_logic... No zustanu u verilogu, zrovna, kdyz se mi to 
> zacalo libit... :D
>
> Dne 19.04.2021 v 8:02 balu napsal(a):
>> bit a std_logic su rozne typy. Pri priradovani je zrejme nutne urobit 
>> konverziu. Alebo este lepsie, ak nie je explicitny dovod pouzit bit, 
>> treba pouzivat signaly len rovnakeho typu (napr. std_logic a 
>> std_logic_vector). Pravdepodobne nieco ako To_Std_Logic(), nikdy som 
>> to osobne nepouzil.
>>
>> Tu je potom uzitocny diagram pre vektory 
>> https://www.doulos.com/knowhow/vhdl/vhdl-vector-arithmetic-using-numeric_std/
>>
>>
>>
>> On 19/04/2021 07:33, Jaroslav Buchta wrote:
>>> Ja uz teda nevim, evidentne nejde priradit bit do std_logic_vector.
>>> Treba takhle to jde:
>>>
>>>     binout(7 downto 1) <= citac(3 downto 0) & 
>>> conv_std_logic_vector(states'pos(state), 3);
>>>     IF led1 = '1' THEN
>>>         binout(0 downto 0) <= "1";
>>>     ELSE
>>>         binout(0 downto 0) <= "0";
>>>     END IF;
>>>
>>> nebo takhle:
>>>     IF led1 = '1' THEN
>>>         binout(0) <= '1';
>>>     ELSE
>>>         binout(0) <= '0';
>>>     END IF;
>>> to celkem dava smysl, pole do pole nebo bit na jednu pozici
>>>
>>> takhle uz ne:
>>>     binout(0 downto 0) <= led1;
>>> Error (10476): VHDL error at nhk_15_buchta_v1.vhd(201): type of 
>>> identifier "led1" does not agree with its usage as 
>>> "std_logic_vector" type
>>> ani
>>>     binout(0) <= led1;
>>> Error (10476): VHDL error at nhk_15_buchta_v1.vhd(201): type of 
>>> identifier "led1" does not agree with its usage as "std_ulogic" type
>>>
>>> Tohle by vypadalo nadejne, to by slo asi i do spojeni  ale taky nejde
>>>     binout(0 downto 0) <= "1" when (led1 = '1') else "0";
>>> Error (10500): VHDL syntax error at nhk_15_buchta_v1.vhd(201) near 
>>> text "when";  expecting ";"
>>>
>>> Asi je problem v konverzi typu bit na neco kompatibilniho se 
>>> std_logic? Prece nemuze byt takovy problem pripojit nebo nastavit 
>>> bit do vektoru...
>>>