STM32F3 ADC
Jaroslav Buchta
jaroslav.buchta na hascomp.cz
Úterý Prosinec 18 17:06:54 CET 2018
Asi blbost, ale uz do RM koukam par hodin - napovi nekdo, proc se s
prilozenym inicializacnim kodem ADC12 nerozbehnou? Maji bezet v
simultalnim modu, spolecne DMA 32b, myslim, ze by to melo stacit spustit
softwarove a cyklicky by mel trvale bezet.
Do ISR od DMA1ch1 to ale vubec nevleze.
ErrorStatus status;
/* Peripheral clock enable */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ADC12);
/* Peripheral clock enable */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ADC34);
LL_DMA_DeInit(DMA1, LL_DMA_CHANNEL_1);
LL_ADC_CommonDeInit(ADC12_COMMON);
LL_ADC_CommonDeInit(ADC34_COMMON);
/* Peripheral clock enable */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ADC12);
/* Peripheral clock enable */
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_ADC34);
LL_GPIO_InitTypeDef GPIO_InitStruct;
LL_GPIO_StructInit(&GPIO_InitStruct);
/**ADC1 GPIO Configuration
PC0 ------> ADC1_IN6
PC1 ------> ADC1_IN7
PC2 ------> ADC1_IN8
PC3 ------> ADC1_IN9
*/
GPIO_InitStruct.Pin =
LL_GPIO_PIN_0|LL_GPIO_PIN_1|LL_GPIO_PIN_2|LL_GPIO_PIN_3;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/**ADC2 GPIO Configuration
PA6 ------> ADC2_IN3
PA7 ------> ADC2_IN4
PC4 ------> ADC2_IN5
PC5 ------> ADC2_IN11
PB2 ------> ADC2_IN12
*/
GPIO_InitStruct.Pin = LL_GPIO_PIN_6|LL_GPIO_PIN_7;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = LL_GPIO_PIN_4|LL_GPIO_PIN_5;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = LL_GPIO_PIN_2;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
LL_ADC_InitTypeDef ADC_InitStruct;
LL_ADC_StructInit(&ADC_InitStruct);
ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_LEFT;
ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
status = LL_ADC_Init(ADC1, &ADC_InitStruct);
if (status != SUCCESS) Error_Handler();
status = LL_ADC_Init(ADC2, &ADC_InitStruct);
if (status != SUCCESS) Error_Handler();
LL_ADC_REG_InitTypeDef ADC_REG_InitStruct;
LL_ADC_REG_StructInit(&ADC_REG_InitStruct);
ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS;
ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_CONTINUOUS;
ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_UNLIMITED;
ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
status = LL_ADC_REG_Init(ADC1, &ADC_REG_InitStruct);
if (status != SUCCESS) Error_Handler();
LL_ADC_DisableIT_EOC(ADC1);
LL_ADC_DisableIT_EOS(ADC1);
status = LL_ADC_REG_Init(ADC2, &ADC_REG_InitStruct);
if (status != SUCCESS) Error_Handler();
LL_ADC_DisableIT_EOC(ADC2);
LL_ADC_DisableIT_EOS(ADC2);
LL_ADC_CommonInitTypeDef ADC_CommonInitStruct;
LL_ADC_CommonStructInit(&ADC_CommonInitStruct);
ADC_CommonInitStruct.CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
ADC_CommonInitStruct.Multimode = LL_ADC_MULTI_DUAL_REG_SIMULT;
ADC_CommonInitStruct.MultiDMATransfer =
LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B;
ADC_CommonInitStruct.MultiTwoSamplingDelay =
LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
status = LL_ADC_CommonInit(ADC12_COMMON, &ADC_CommonInitStruct);
if (status != SUCCESS) Error_Handler();
//Configure Regular Channels ADC1
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1,
LL_ADC_CHANNEL_6);
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_6,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_6,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_2,
LL_ADC_CHANNEL_7);
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_7,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_7,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_3,
LL_ADC_CHANNEL_8);
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_8,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_8,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_4,
LL_ADC_CHANNEL_9);
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_9,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_9,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_5,
LL_ADC_CHANNEL_6);
LL_ADC_SetChannelSamplingTime(ADC1, LL_ADC_CHANNEL_6,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC1, LL_ADC_CHANNEL_6,
LL_ADC_SINGLE_ENDED);
//Configure Regular Channels ADC2
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_1,
LL_ADC_CHANNEL_3);
LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_3,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_3,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_2,
LL_ADC_CHANNEL_4);
LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_4,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_4,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_3,
LL_ADC_CHANNEL_5);
LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_5,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_5,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_4,
LL_ADC_CHANNEL_11);
LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_11,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_11,
LL_ADC_SINGLE_ENDED);
LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_5,
LL_ADC_CHANNEL_12);
LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_12,
LL_ADC_SAMPLINGTIME_4CYCLES_5);
LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_12,
LL_ADC_SINGLE_ENDED);
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(ADC1);
LL_ADC_EnableInternalRegulator(ADC2);
/* Delay for ADC internal voltage regulator
stabilization. */
/* Compute number of CPU cycles to wait for, from delay in
us. */
/* Note: Variable divided by 2 to compensate
partially */
/* CPU processing cycles (depends on compilation
optimization). */
static volatile int wait_loop_index;
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US *
(SystemCoreClock / (100000 * 2))) / 10);
while(wait_loop_index != 0)
{
wait_loop_index--;
}
LL_ADC_StartCalibration(ADC1, LL_ADC_SINGLE_ENDED);
LL_ADC_StartCalibration(ADC2, LL_ADC_SINGLE_ENDED);
while (LL_ADC_IsCalibrationOnGoing(ADC1) ||
LL_ADC_IsCalibrationOnGoing(ADC2));
/* Delay between ADC end of calibration and ADC
enable. */
/* Note: Variable divided by 2 to compensate
partially */
/* CPU processing cycles (depends on compilation
optimization). */
wait_loop_index = 50;
while(wait_loop_index != 0)
{
wait_loop_index--;
}
// setup DMA to transfer, ADC1
LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1,
LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1,
LL_DMA_PRIORITY_VERYHIGH);
LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_CIRCULAR);
LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1,
LL_DMA_PERIPH_NOINCREMENT);
LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1,
LL_DMA_MEMORY_INCREMENT);
LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_WORD);
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_WORD);
LL_DMA_SetPeriphAddress(DMA1, LL_DMA_CHANNEL_1,
(uint32_t)&ADC1_2_COMMON->CDR);
LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_1,
(uint32_t)adc1_dma_buffer);
LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_1, ADC_CHANNELS*2);
LL_DMA_EnableIT_HT(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1);
LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
LL_ADC_Enable(ADC1);
LL_ADC_Enable(ADC2);
LL_ADC_REG_StartConversion(ADC1);
HAL_Delay(10);
HAL_Delay(10);
HAL_Delay(10);
HAL_Delay(10);
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