ESP32 a watchdog

[Jaroslav Buchta]

Tak nevim, asi by se to muselo nejak SW obslouzit, v tech knihovnach i v
dokumentaci je trosku bordel, ehm, casty nesoulad...
Pouzil jsem RTC Watchdog, ktery umi totalni RESET vcetne RTC a to
funguje dobre a nabiha pekne. Jen funkci jsem pochopil spis ze zdrojaku,
nez z dokumentace (v obojim je chyba u FEED bitu)

rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0018,len:4
load:0x3fff001c,len:5744
ho 0 tail 12 room 4
load:0x40078000,len:0
load:0x40078000,len:13164
entry 0x40078e7c

Ty TIMER WDT moduly jsou asi spis pro interrupt nebo reset jednotlivych
jader, defaultni SW obsluha ale nejak uplne nefunguje.
Kdyby to nekomu pomohlo, kod inicializace a obsluhy vypada takto:

#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"

static uint32_t rtc_wdt_value = 150000;

static bool wdt_app_cpu_ticked=false;

static void IRAM_ATTR tick_hook1(void)
{
     wdt_app_cpu_ticked=true;
}

static void IRAM_ATTR tick_hook0(void)
{
     if (wdt_app_cpu_ticked)
     {
         RTCCNTL.wdt_wprotect = RTC_CNTL_WDT_WKEY_VALUE;
         RTCCNTL.wdt_config1 = rtc_wdt_value;
         RTCCNTL.wdt_feed.feed = 1;
         RTCCNTL.wdt_wprotect = 0;
         wdt_app_cpu_ticked=false
      }
}




static void rtc_wdt_enable(int time_ms)
{
     RTCCNTL.wdt_wprotect = RTC_CNTL_WDT_WKEY_VALUE;
     RTCCNTL.wdt_feed.feed = 1;
     RTCCNTL.wdt_config0.sys_reset_length = 7;
     RTCCNTL.wdt_config0.cpu_reset_length = 7;
     RTCCNTL.wdt_config0.stg0 = RTC_WDT_STG_SEL_RESET_RTC;
     rtc_wdt_value = rtc_clk_slow_freq_get_hz() * time_ms / 1000;
     RTCCNTL.wdt_config1 = rtc_wdt_value;
     RTCCNTL.wdt_config0.en = 1;
     RTCCNTL.wdt_config0.pause_in_slp = 1;
     RTCCNTL.wdt_wprotect = 0;
     WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
}


a nekde v app_main:

     rtc_wdt_enable(1000);
     esp_register_freertos_tick_hook_for_cpu(tick_hook0, 0);
     esp_register_freertos_tick_hook_for_cpu(tick_hook1, 1);


Dne 30.12.2017 v 10:47 David Obdrzalek napsal(a):
> S problemem proc watchdog nesteka jak ma bohuzel neporadim, ale rozsypany caj bude
> jiny baudrate. Tak si v terminalu nastavte rychlost jinak a treba z toho textu pak
> pujde neco vysoudit. I kdyz proc se to zakousne asi ne, kdyz to je vypis zze
> situace, kdyz se to podari. (lepsi by byl logicky analyzator nez terminal, dalo by
> se na dvou kanalech nastavit ty dve ruzne rychlosti)
>
> D.O.
>
> On 29 Dec 2017 at 18:27, Jaroslav Buchta wrote:
>> *Mam problem s nejistym restartem, selze tak v 15% pripadu, boot se
>> sekne asi takto.*
>>
>>    Jun  8 2016 00:22:57
>>
>> rst:0x8 (TG1WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
>> configsip: 0, SPIWP:0xee
>> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
>> mode:DIO, clock div:2
>> load:0x3fff0018,l    .... a slus
>>
>> *Kdyz nabehne, tak to po  WD vypada takto, divna je ta sekvence
>> rozsypaneho caje a opakovani nekterych vypisu... Navic je to pokazde
>> jine, ale mozna z toho blbne terminal*
>>
>> Jun  8 2016 00:22:57
>>
>> rst:0x8 (TG1WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
>> configsip: 0, SPIWP:0xee
>> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
>> mode:DIO, clock div:2
>>
>> load:0x3fff0018,l03`x<`<x
>>                             xxx<x
>>                                     fAE03``
>> ff  03`x<`<
>>                                            
>>                   ?x
>> load:0x3fff0018,l03`x<`<x <<fAE03`x<`<
>>                             xxx<x
>>                                     fAE03``
>> ff  03`x<`<
>>                                            
>>                   ?x
>> <<fAE03`x<`<
>> ?x
>> <<fAEx
>> x
>> 03``??
>>
>> ?x
>> x3`f ~xxf0f f 3~<f?? 3f ffffAE<~
>>                                         
>> 30ff
>> x3`f ~xxf0f f 3~<f?? 3f ffffAE<~      W (75) boot: PRO
>> CPU has
>> been reset by WD
>>                                         
>> 30ff
>>                                            
>>     W (75) boot: PRO CPU has
>> been reset by WDT.
>> W (75) boot: WDT reset info: PRO CPU PC=0x40104294
>> 0x40104294: btn_rel_action at
>> D:/Work/_Esp32/workspace/TestTFT/main/spi_master_example_main.c:223
>> (discriminator 1)
>>
>> W (75) boot: WDT reset info: APP CPU PC=0x400d162a (waiti mode)
>> 0x400d162a: esp_vApplicationIdleHook at
>> C:/Esp32/esp-idf/components/esp32/freertos_hooks.c:85
>>
>> *Normalne reset tlacitkem vypada takto:*
>>
>> Jun  8 2016 00:22:57
>>
>> rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
>> configsip: 0, SPIWP:0xee
>> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
>> mode:DIO, clock div:2
>> load:0x3fff0018,len:4
>> load:0x3fff001c,len:5856
>> ho 0 tail 12 room 4
>> load:0x40078000,len:0
>> load:0x40078000,len:14328
>> entry 0x40078fd4
>>
>> *Nebojoval s tim uz nekdo, ze by poradil, kde je zakopany pes?*
>>
>>
>
>
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