VHDL - hloupe otazky 2.0

balu@home balu na k-net.fr
Pátek Leden 3 23:20:43 CET 2014


nebude jednoduchsie tu RAM bezat na dvojnasobku 65MHz?


On 03/01/2014 23:18, hw na itherm.cz wrote:
> Jde o to ze potrebuju generovat vga obraz 1024x768 ktery ma pixel clock 65MHz
>
> Data pro vga se musi vycitat z SRAMa tam ale potrebuju udelat cca 5 operaci s 10ns ram a to tech 65MHz je malo, protoze to nestihnu za jeden pixel.
>
> Pavel
>
>
> -----Original Message-----
> From: Hw-list [mailto:hw-list-bounces na list.hw.cz] On Behalf Of balu na home
> Sent: 3. ledna 2014 23:05
> To: HW-news
> Subject: Re: VHDL - hloupe otazky 2.0
>
> zalezi co od toho ocakavate...
> Ak potrebujete kvalitne hodiny tak ich treba po cipe rozvadzat dedikovanymi hodinovymi zbernicami. To sa sposobom uvedenym dole neda (pouzijem hodinovu zbernicu pre logiku a ta bude generovat odvodene hodiny, tieto sa budu ale rozvadzat len beznym routovanim).
> Vacsina FPGA ma na cipe obvody sluziace na upravu hodin. Treba instancovat vhodny primitiv a mate to zadarmo. Najdete oneskorovacie linky, fazove zavesy, oneskorovacie zavesy a ine. Asi by som sa v prvom rade pozrel tymto smerom.
> Mozno musia byt obidve frekvencie perfektne nizkosumove, mozno tych odvodenych 65MHz moze byt robenych len nejakym clock enable na 100MHz domene. Mozno by nebolo zle naznacit konecnu aplikaciu.
> b.
>
>
> On 03/01/2014 22:40, Draček Fráček wrote:
>> Jsem asi ten posledni , dko tu muze radit ve VHDL, neb je to pro me
>> pueblo español, presto.
>> Ono zalezi na jakem HW to pak pojede a predevsim jak haklivy jste na
>> presnsot a stridu hodin.
>> Pokud nejste cimprlich tak, timhle by pri M=13 a D=20 mohlo jit udelat
>> 65 z 100
>>
>> -- =======
>> --
>> -- Given:
>> --
>> --   Fi = input frequency Hz
>> --   M  = multiplier
>> --   D  = divisor
>> --   Fo = output frequency Hz
>> --
>> -- Where:
>> --
>> --   M ≤ D
>> --
>> -- Then:
>> --
>> --        ⎧    M
>> --        ⎪ Fi·—        if M <= D
>> --   Fo = ⎨    D
>> --        ⎪
>> --        ⎩ undefined   if M > D
>> --
>> --
>> -- If (M/D) is greater than 0.5, only the clock enable is valid.
>> -- If (M/D) is greater than 1.0, both outputs are invalid.
>>
>> entity Clock_Divider is
>>     generic (
>>       operand_width : positive
>>       );
>>     port (
>>       clock : in bit;
>>       reset : in bit;
>>
>>       multiplier : in unsigned(operand_width-1 downto 0);
>>       divisor    : in unsigned(operand_width-1 downto 0);
>>
>>       out_enable : buffer bit;
>>       out_clock  : buffer bit
>>       );
>> end entity;
>>
>> architecture any of Clock_Divider is
>>     signal enable_2x : bit;
>> begin
>>
>>     -- Divide the clock by accumulating phase using the mulitplier and
>>     -- subtracting when we pass the divisor value.
>>
>>     proc_enable : process is
>>       variable phase : unsigned(operand_width downto 0);
>>     begin
>>       wait until rising_edge(clock);
>>       phase := phase + multiplier;
>>       if phase >= divisor then
>>         phase := phase - divisor;
>>         out_enable <= '1';
>>       else
>>         out_enable <= '0';
>>       end if;
>>       if reset = '1' then
>>         phase := (others => '0');
>>         out_enable <= '0';
>>       end if;
>>     end process;
>>
>>     proc_enable : process is
>>       variable phase : unsigned(operand_width downto 0);
>>     begin
>>       wait until rising_edge(clock);
>>       phase := phase + (multiplier & '0');
>>       if phase >= divisor then
>>         phase := phase - divisor;
>>         enable_2x <= '1';
>>       else
>>         enable_2x <= '0';
>>       end if;
>>       if reset = '1' then
>>         phase := (others => '0');
>>         enable_2x <= '0';
>>       end if;
>>     end process;
>>
>>
>>     proc_out_clock : process is
>>     begin
>>       wait until rising_edge(clock);
>>       if enable_2x = '1' then
>>         out_clock <= not out_clock;
>>       end if;
>>     end process;
>>
>> end architecture;		
>>
>>
>>
>> Dne 3. ledna 2014 21:14 <hw na itherm.cz <mailto:hw na itherm.cz>> napsal(a):
>>
>>      Mam dalsi otazku ;-)
>>
>>      Potreboval bych generovat 65MHz a 100MHz hodiny, da se to udelat pomoci
>>      jednech hodin z venku?
>>
>>      Pavel
>>
>>
>>      -----Original Message-----
>>      From: Hw-list [mailto:hw-list-bounces na list.hw.cz
>>      <mailto:hw-list-bounces na list.hw.cz>] On Behalf Of Marek Peca
>>      Sent: 2. ledna 2014 10:13
>>      To: HW-news
>>      Subject: RE: VHDL - hloupe otazky
>>
>>       > Me pri otazce slo hlavne o to jestli neni nejaky jeste lepsi postup
>>       > nez stavovy automat.
>>
>>      To je velmi zapeklita otazka. Z hlediska Turingovske ekvivalence
>>      automatu je
>>      v synchronnim svete uplne *kazdy* obvod na spolecnem hodinovem signalu
>>      stavovym automatem...
>>
>>      Prakticky zajimave jsou tedy 2 rozdilne dusledky zpusobu psani v HDL:
>>      a) co vyjde dobre na cas, popr. spotrebu hradel
>>      b) co se dobre cte a pise
>>
>>       > Premyslel jsem nad tim to udelat i jako velky posuvny registr a
>>      proste
>>       > to precist najednou ;-)
>>
>>      V a) to pro vetsinu uloh vyjde nevyhodne, velmi brzo pomine i
>>      zdanlive b),
>>      obavam se.
>>
>>
>>      ZdraviMP
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>>
>>
>>
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