zapis do textoveho suboru vo VHDL

[Daniel Valuch]

trochu zapasim so zapisom dat do textoveho suboru a neviem ani najst 
ziaden vhodny priklad na internete ktory by sa dal vykradnut :-)
Do mojho dizajnu chcem vlozit blok, ktory mi pocas simulacie bude do 
textoveho suboru zapisovat hodnoty signalov aby som ich mohol neskor 
spracovat povedzme v exceli.
Mam zatial toto:


library ieee;
use ieee.STD_LOGIC_1164.all;
library std;
use std.textio.all;


entity  FileWrite  is
port (clk : in std_logic ;
       rst : in std_logic);
end;

architecture  FileWrite  of  FileWrite  is

begin
    write_file:
     process is
       file my_output : TEXT open WRITE_MODE is "c:\file_io.out";
       variable my_line : LINE;
       variable my_output_line : LINE;
     begin
       wait until Rising_edge(clk);
         write(my_output_line, string'("writing string"));
         writeline(my_output, my_output_line);
         write(my_output_line, clk);
         writeline(my_output, my_output_line);
     end process write_file;

end;

prva cast funguje a do textoveho suboru sa mi skutocne pri kazdom 
hodinovom pulze zapise text "writing string". Bohuzial druha cast 
vyhadzuje chybu "ERROR: The actual associated with 
parameter/port/generic VALUE does not match in 
TransvPos_top:FileWrite.FileWrite.FileWrite.FileWrite #25 "
co predpokladam ze znamena ze signal nie je spravne naformatovany. Vie 
mi niekto povedat co s tym prosim?
dik,
b.