simulacia v ise7.1

["Ing. Zbyněk HEJDA"]

Dobry den,
v priloze posilam test soubor pro otestovani citace. Pro vitvoreni
vstupniho "clk" je dulezita rutina s navestim "tb".

tb : PROCESS
     BEGIN
        for i in 0 to 100 loop
          CLK <= '1';
          wait for 5 ns; --doba trvani stavu H
          CLK <= '0';
          wait for 5 ns; -- doba trvani stavu L
      end loop;
   end process;

-- 
Electrical designer
Ing. Zbynek Hejda
RAMET C.H.M. a.s.
Letecka 1110
686 04 Kunovice
Czech Republik
tel: +420572415281
e-mail: zbynek_hejda@rametchm.cz
www: www.rametchm.cz

------------- další část ---------------
An embedded and charset-unspecified text was scrubbed...
Name: test.vhd
Url: http://list.hw.cz/pipermail/hw-list/attachments/20060222/9c7b5be5/attachment.txt