VHDL - obousmerna sbernice

[Petr Sremr]

> WARNING:Xst:766 - D:/Projects/Logic_01/jspp/jspp1/jspp1.vhd (Line 56). 
> Generating a Black Box for component <obufe>.
> WARNING:Xst:766 - D:/Projects/Logic_01/jspp/jspp1/jspp1.vhd (Line 60). 
> Generating a Black Box for component <ibuf>.
 >
>      output : OBUFE
>          port map (O => D,
>                    E => en,
>                    I => r);
>      input : IBUF
>          port map (O => i,
>                    I => D);
> 
>      pr_1: process (E)
>      begin
>          if (E'event and E = '0') then
>              if (RW = '0') then
>                  r <= i;
>              end if;
>          end if;
>          en <= RW and not E;
>      end process;

jeste drobna uprava. Takto by to podle me melo fungovat. Ale prvni ty 
upozorneni mi tam stejne zustavaji...

     pr_1: process (E)
     begin
         if (E'event and E = '0') then
             if (RW = '0') then
                 r <= i;
             end if;
         end if;
     end process;

     en <= RW and not E;

> end moje_architektura;

--
Petr Sremr
HW group