VHDL - obousmerna sbernice

Danhard danhard@volny.cz
Pátek Duben 21 14:58:14 CEST 2006


Paneboze! zlatej ABEL, tam je to napsany snad na tri radky :o))

Danhard
*******

Co to nadratovat ve VHDL primo ?

Tomas Svoboda

nasel jsem nejaky muj modul kde jsem neco podobneho delal.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity IdePort16 is
     port (
  dataidx:inout std_logic_vector(15 downto 0);
  datadov: out std_logic_vector(15 downto 0) ;
  dataven: in  std_logic_vector(15 downto 0);
  dataT:in std_logic);
end IdePort16;

architecture Behavioral of IdePort16 is

 component OBUFT -- vystup T=1 je vysoka impedance
port (
       I : in std_logic;
       T : in std_logic;
       O : out std_logic);
end component;

component IBUF
port (
       I : in std_logic;
       O : out std_logic);
end component;

begin
veno0: OBUFT port map (i => dataven(0) ,O => dataidx(0) ,T =>dataT
); veno1: OBUFT port map (i => dataven(1) ,O => dataidx(1) ,T
=>dataT ); veno2: OBUFT port map (i => dataven(2) ,O => dataidx(2)
,T =>dataT ); veno3: OBUFT port map (i => dataven(3) ,O =>
dataidx(3) ,T =>dataT ); veno4: OBUFT port map (i => dataven(4) ,O
=> dataidx(4) ,T =>dataT ); veno5: OBUFT port map (i => dataven(5)
,O => dataidx(5) ,T =>dataT ); veno6: OBUFT port map (i =>
dataven(6) ,O => dataidx(6) ,T =>dataT ); veno7: OBUFT port map (i
=> dataven(7) ,O => dataidx(7) ,T =>dataT ); veno8: OBUFT port map
(i => dataven(8) ,O => dataidx(8) ,T =>dataT ); veno9: OBUFT port
map (i => dataven(9) ,O => dataidx(9) ,T =>dataT ); venoa: OBUFT
port map (i => dataven(10) ,O => dataidx(10) ,T =>dataT ); venob:
OBUFT port map (i => dataven(11) ,O => dataidx(11) ,T =>dataT );
venoc: OBUFT port map (i => dataven(12) ,O => dataidx(12) ,T
=>dataT ); venod: OBUFT port map (i => dataven(13) ,O =>
dataidx(13) ,T =>dataT ); venoe: OBUFT port map (i => dataven(14)
,O => dataidx(14) ,T =>dataT ); venof: OBUFT port map (i =>
dataven(15) ,O => dataidx(15) ,T =>dataT ); dovni0 : IBUF port map
(i => dataidx(0) ,O => datadov(0));
dovni1 : IBUF port map (i => dataidx(1) ,O => datadov(1));
dovni2 : IBUF port map (i => dataidx(2) ,O => datadov(2));
dovni3 : IBUF port map (i => dataidx(3) ,O => datadov(3));
dovni4 : IBUF port map (i => dataidx(4) ,O => datadov(4));
dovni5 : IBUF port map (i => dataidx(5) ,O => datadov(5));
dovni6 : IBUF port map (i => dataidx(6) ,O => datadov(6));
dovni7 : IBUF port map (i => dataidx(7) ,O => datadov(7));
dovni8 : IBUF port map (i => dataidx(8) ,O => datadov(8));
dovni9 : IBUF port map (i => dataidx(9) ,O => datadov(9));
dovnia : IBUF port map (i => dataidx(10) ,O => datadov(10));
dovnib : IBUF port map (i => dataidx(11) ,O => datadov(11));
dovnic : IBUF port map (i => dataidx(12) ,O => datadov(12));
dovnid : IBUF port map (i => dataidx(13) ,O => datadov(13));
dovnie : IBUF port map (i => dataidx(14) ,O => datadov(14));
dovnif : IBUF port map (i => dataidx(15) ,O => datadov(15));
end Behavioral;

> Zdravim,
> 
> pred casem jsem se pokusel pro XILINX CPLD XC9536XL ve VHDL
> napsat 
> obousmernou sbernici pro komunikaci s procesorem s rozhranim:
> 
> - D0, D1,..., D7
> - WR, RD
> 
> Po nekolika vecerech pokusu jsem dospel k tomu, ze jsem si
> znicil obe 
> CPLDcka, ktere jsem mel k dispozici.
> 
> Tak jsem si koupil novy a zkusil jsem Abel. V nem jsem to
> napsal bez 
> problemu.
> 
> Ale potrebuju to pro VHDL, protoze celou aplikaci chci napsat
> ve VHDL. 
> Tentokrat jde o XC95288XL.
> 
> Jak to v tom VHDL napsat??? Dekuju.
> 
> --
> Petr Sremr
> HW group





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