VHDL, scitacka a CarryOut

[Milan]

Ja to skonkretizujem, napr.

   signal AddReg: std_logic_vector (7 downto 0);
   signal CntAdd: std_logic_vector (8 downto 0);

   CntAdd <= AddReg & '0';
        alebo podla potreby napr:
   CntAdd <= AddReg(7 downto3) & '1' & AddReg(2 downto0);

Milan
----- Original Message ----- 
From: "Daniel Valuch" <daniel.valuch@wanadoo.fr>
To: "HW-news" <hw-list@list.hw.cz>
Sent: Thursday, April 20, 2006 9:31 AM
Subject: Re: VHDL, scitacka a CarryOut


naformatujte si ten 8 bitovy vektor do 9 bitoveho tak ze MSB bude nula 
(spojite 8 bitovy vektor a konstantu '0'). Potom scitate, viete ze k 
preteceniu nemoze dojst a viete ze MSB bude carry out. Nemam tu moje 
poznamky (som v Bratislave), takze konkretne vam neporadim.
Jedna zo zakladnych vlastnosti VHDL je jednoznacnost. Pri vsetkych 
operaciach mozete pouzivat len rovnake (alebo definovane) operandy. 
Zamedzi sa tym veciam typu sucet signed a unsigned vektora a podobne.
b.

p.s. nemali by byt vsetky operacie vo vnutri procesu?


Hynek Sladky wrote:

>Uz zas nevim, jak dal. Potrebuju dostat signal CarryOut ze scitacky, ale 
>nejak se nedari...
>
>mam registr
>   signal AddReg: std_logic_vector (7 downto 0) := "10000000";
>dale vysledek
>   signal CntAdd: std_logic_vector (8 downto 0);
>a operace
>   CntAdd <= Cnt + AddReg;
>   process (Fin) begin
>     if (Fin='1' and Fin'event) then
>       Cnt <= CntAdd(7 downto 0);
>     end if;
>   end process;
>
>Myslel jsem, ze CntAdd(8) bude obsahovat CarryOut, ale zda se, ze ne.
>Preklad vyhodi Warning:
>Width mismatch. <CntAdd> has a width of 9 bits but assigned expression 
>is 8-bit wide.
>
>Jak by se to dalo vyresit?
>
>Diky,
>Hynek Sladky
>  
>


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