Hranovy RESET ve VHDL na 9572

[Milan]

Mozno som to mal napisat konkretnejsie:

  process(CLK, RST, rst_l, CNT)
  begin
     if rising_edge (CLK) then      ;;; resp. ((CLK)'event and(CLK) = '0')
       rst_l<= RST;                       ;;; oneskorenie o 1 CLK
       if (RST='1')and(rst_l='0') then       ;;; nabezna hrana
         CNT<=0;
       else
         CNT<=CNT+1;
       end if;
    else
       rst_1<=rst_1;                      ;;; netreba, ale predsa
    end if;
  end process;

Pozor signal RST uz musi byt zasynchronizovany /musi ist cez klopak s tymi 
istymi hodinami/ nie priamo zo vstupneho pinu!!!
t.j:

  process(CLK, RST, rst_l, rst_2, CNT)
  begin
     if rising_edge (CLK) then      ;;; resp. ((CLK)'event and(CLK) = '0')
       rst_l<= RST;                       ;;; synchronizacia
       rst_2<= rst1;                       ;;; oneskorenie o 1 CLK
       if (rst_1='1')and(rst_2='0') then       ;;; nabezna hrana
         CNT<=0;
       else
         CNT<=CNT+1;
       end if;
    else
       rst_1<=rst_1;                      ;;; netreba, ale predsa
       rst_2<=rst_2;                      ;;; netreba, ale predsa
    end if;
  end process;

Milan

----- Original Message ----- 
From: "Milan" <milger@pobox.sk>
To: "HW-news" <hw-list@hw.cz>
Sent: Friday, February 25, 2005 11:05 AM
Subject: Re: Hranovy RESET ve VHDL na 9572


Treba napisat detektor hrany:

  process(CLK, PG, pg_l,rst)
  begin
     if rising_edge (CLK) then                  ;;; resp. ((CLK)'event and
(CLK) = '0')
       pg_l<= PG;                                     ;;; oneskorenie 1 CLK
       if (PG='1')and(pg_l='0') then           ;;; nabezna hrana
         rst <= '1';

         OUT<='0';
       else
         rst <= '0';

         OUT<='1';                                   ;;; resp. OUT<=OUT
atd...
       end if;
    end if;
    if (rst='1') then                                  ;;;signal rst sa da
samozrejme vyuzit aj ako asynchronny vstup
       OUT1<='0';
    else
       OUT1<='1';                                   ;;; resp. OUT1<=OUT1
atd...
    end if;
  end process;

Toto je samozrejme synchronny zapis. Niekedy samozrejme ide pouzit aj
asynchronne riesenie, pokial netreba dalsie hodiny:

  process(PG)
  begin
     if rising_edge (PG) then                  ;;; resp. ((PG)'event and
(PG) = '0')
       OUT <= '0';
     else
       OUT <= '1';                                  ;;; resp. OUT<=OUT
atd...
    end if;
  end process;

Mozno som sa pomylil, ale pointa je jasna!


Milan

----- Original Message ----- 
From: <j.vohanka@email.cz>
To: <hw-list@hw.cz>
Sent: Friday, February 25, 2005 10:25 AM
Subject: Hranovy RESET ve VHDL na 9572


Dobry den,
nejsem si uplne jist, jestli to tu nekdy uz nebylo...
nevite nekdo, jak lze co nejjednoduseji napsat ve VHDL napr. citac, ktery
lze resetovat hranou(napr.sestupnou), tak aby v libovolne urovni Resetu
cital?

S diky, Easy


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