Xilinx, verilog - problem

[Jakub Ladman]

> asi neco takovehle, ale verilog neumim !!!!
>    always @(posedge  clk or edge reset)
>       if (reset)
>          out <= 0;
>       else if (posedge clk)
>          out <= out + 1;
>
To vypada dobre, vcetne verilog syntaxe :-) jdu to zkusit.
Jakub