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<div class="moz-cite-prefix">Zkuste nejakou starsi verzi, pro tyhle
prehistoricke obvody je to asi uplne jedno. Uz jsem s tim dlouho
nedelal, ale pouzival jsem taky rok-2 starou verzi, nakonec kazda
nova je vzdy pomalejsi, sezere vic disku, odstrani n chyb a prida
n+x, x>0 chyb ;-)<br>
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<div class="moz-cite-prefix">Dne 17.12.2024 v 16:40 Marek Sembol
napsal(a):<br>
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<blockquote type="cite"
cite="mid:CADUfZ8G5oH2LY84=7CfoNvVm3tNMzueSyCRZd4=+now3W=DrLA@mail.gmail.com">
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<div dir="ltr">Ahoj, diky, ale nepomuze. Zkousel jsem pouzit
vsechny vstupy i vystupy a pada to uplne stejne. To co jsem
publikoval byl 'minimalni padajici stav'
<div>BR,</div>
<div>Marek</div>
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<br>
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<div dir="ltr" class="gmail_attr">On Tue, Dec 17, 2024 at
4:14 PM Jan Waclawek <<a href="mailto:konfera@efton.sk"
moz-do-not-send="true" class="moz-txt-link-freetext">konfera@efton.sk</a>>
wrote:<br>
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<blockquote class="gmail_quote"
style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">[preposielam]<br>
<br>
Ahoj,<br>
<br>
som sice iba amater vo verilogu, ale po precitani knizky o
Verilogu,<br>
introduction to verilog pdf a zhliadnuti nejakych video kuzrov
na YT si<br>
muslim, ze Ti v tom module chyba priradenie logickej funkcie,
nieco ako<br>
napriklad:<br>
<br>
assign beep <= Clock_50M;<br>
<br>
Potom by Ta to uz malo pustit ku priradeniu pinov a floor
planing. Ale<br>
dalej som sa v manuale ku Quartus-u a Verilogu nedocital. Tak
snad Ti to<br>
pomoze.<br>
<br>
A.<br>
<br>
>>><br>
<br>
Predem dik,<br>
Marek<br>
<br>
module QuartusTest(<br>
input Clock_50M,<br>
input [7:0] nKey,<br>
input [7:0] SW,<br>
input uart_rx,<br>
output uart_tx,<br>
output beep,<br>
output [15:0] Led,<br>
output [1:6] nSegEn,<br>
output [7:0] SegSegment,<br>
inout [2:22] gpio_p1,<br>
inout [2:22] gpio_p2,<br>
input gpio_clk,<br>
inout [4:38] gpio<br>
);<br>
<br>
endmodule<br>
<br>
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