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<body>Toto tu podla mna nie je vysvetlenie a prestavenie do Device zakryva nejaky iny mechanizmus (a ani zapnuta cache by to podla mna nevysvetlila). <br><br>Ak by sa to stalo pri citani (co viem ze sa stava) tak to je v poriadku, to je z pohladu Normal pamate koser, ale zapis nie, ved to nepochybne poskodi obsah pamate.<br><br>Mohli by to pritomni experti z ST prosim okomentovat?<br><br>Dakujem<br><br>wek<br><br><div class="gmail_quote">On 6 May 2020 09:51:21 CEST, Jaroslav Buchta <jaroslav.buchta@hascomp.cz> wrote:<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div class="moz-cite-prefix">Aha, tak jsem zapomel zase na ruzne
typy pristupu do pameti, device memory atd... <br>
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<div class="moz-cite-prefix">Resi to remap a bude to snad resitelne
i konfigurtaci MMU.</div>
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<div class="moz-cite-prefix"><a class="moz-txt-link-freetext" href="https://community.st.com/s/question/0D50X00009XkWQE/stm32h743ii-fmc-8080-lcd-spurious-writes">https://community.st.com/s/question/0D50X00009XkWQE/stm32h743ii-fmc-8080-lcd-spurious-writes</a></div>
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<div class="moz-cite-prefix">Dne 06.05.2020 v 8:33 Jaroslav Buchta
napsal(a):<br>
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<blockquote type="cite" cite="mid:f40db596-04ae-6491-871f-399688ce0855@hascomp.cz">Mam na
FMC pripojeny OLED displej, 8b dat, konfigurace pres CubeMX.
DCACHE MCU zakazana.
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<br>
Kdyz provedu radek
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*(volatile uint8_t *)0x60010000 = 0xaa;
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vyvola to 2x NE1 a v kazdem cyklu 4x NWE
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V Assembleru to vypada OK
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237 *(volatile uint8_t *)0x60010000 = 0xaa;
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08000bf8: ldr r3, [pc, #24] ; (0x8000c14 <main+172>)
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08000bfa: movs r2, #170 ; 0xaa
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08000bfc: strb r2, [r3, #0]
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<br>
Konfigurace je jako LCD interface 8 bitu. FIFO zakazana. Stejne se
to chova pri krokovani jako pri normalnim behu.
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jednotlivy zapis vypada z hlediska NWE dle obrazku v priloze.
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Napada nekoho, kde muze byt problem?
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