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tu mate k tomu priklad (zvyraznene riadky):<br>
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library IEEE;<br>
use IEEE.Std_logic_1164.all;<br>
use IEEE.Numeric_std.all;<br>
<br>
entity Counter is<br>
port (Clock, Reset, Enable, Load, UpDn: in Std_logic;<br>
Data: in Std_logic_vector(7 downto 0);<br>
Q: out Std_logic_vector(7 downto 0));<br>
end;<br>
<br>
architecture RTL of Counter is<br>
<b> signal Cnt: Unsigned(7 downto 0);</b><br>
begin<br>
process (Clock, Reset)<br>
begin<br>
if Reset = '1' then<br>
Cnt <= "00000000";<br>
elsif Rising_edge(Clock) then<br>
if Enable = '0' then<br>
null;<br>
elsif Load = '1' then<br>
<b> Cnt <= Unsigned(Data);</b><br>
else<br>
if UpDn = '1' then<br>
<b> Cnt <= Cnt + 1;</b><br>
else<br>
Cnt <= Cnt - 1;<br>
end if; <br>
end if;<br>
end if;<br>
end process;<br>
<br>
<b> Q <= Std_logic_vector(Cnt);</b><br>
end;<br>
<br>
<br>
Michal HW wrote:
<blockquote cite="mid000a01c58d29$72b77b50$4700a8c0@Stolni" type="cite">
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