FPGA OpenRISC (bylo Verilog a FPGA (bylo FPGA Altera a NIOS))
Jaroslav Buchta
jaroslav.buchta na hascomp.cz
Úterý Únor 17 14:59:14 CET 2015
No to me napadlo taky, otazka je, jestli to ma vyznam? Kdyz se podivam
na schema, tak to vypada docela logicky a v serii jsou tak max 3-4 LUT,
celkem nezavisle na tom, jak to napisu.
Trosku predpokladam, ze u ciste kombinacni logiky existuji sofistikovane
algoritmy pro jejich optimalizaci a pozadovana funkce dopadne realizacne
vzdy stejne, ne?
Dne 17. 2. 2015 v 9:54 Jan Smrz napsal(a):
> Zdravim,
>
> kod mi neni zcela jasny, takze jsem ho detailne neprochazel. Vidim
> ale, ze tam mate retezeno nekolik sirokych komparatoru a to nikdy
> nebude extra rychle.
>
> Da se trochu pomoci, ze se preferuje pouziti case pred retezci else-if
> apod. Napr zde v prvnim procesu (priority selector) mate vystup 1-hot,
> navazujici process (kde se prirazuji signaly internal_*_ms) uz pak
> muze pouzivat jen case.
>
>
> J.S.
>
>
> On 02/16/2015 11:25 PM, Jaroslav Buchta wrote:
>> Muzete nekdo zkuseny mrknout na to, jak jsem napsal multiplexer
>> sbernic? (nejsou tam zatim vsechny signaly) je to ciste kombinacni
>> logika.
>> Jestli neco neni uplne spatne - princip je ten, ze na interni signaly
>> privedu vystupni signaly z jednoho master a vybraneho slave, adresy a
>> data pak prenasim do vsech cilu (usetri logiku) a jen ridici signaly
>> STB a CYC budu maskovat smerem k SLAVE, smerem k masterum zase ACK,
>> ERR, RTY
>> Podle simulace se zda, ze tam jsou docela velka zpozdeni, ale mam to
>> pres vstupy a vystupy, uvidime v realu... Lze to nejak ovlivnit? At
>> to napisu ruznymi zpusoby, vznikne celkem slozity propletenec LUTs
>> bez nejake pruhledne logiky...
>>
>> Jde mi o posouzeni, jestli nejake konstrukce nejsou uplne spatne nebo
>> jak to udelat lip, prioritou je nenarocna implementace (tahle zatim
>> zabere 111 les, tedy spis LUT, bez registru)
>>
>>
>>
>>
>> module BusMatrix
>> (
>> input wb_clk,
>> input wb_rst,
>>
>> // OR1K Instruction Master
>> input [31:0] or32_i_adr_i,
>> input or32_i_cyc_i,
>> input or32_i_stb_i,
>> output [31:0] or32_i_dat_o,
>>
>>
>> // OR1K Data Master
>> input [31:0] or32_d_adr_i,
>> input or32_d_cyc_i,
>> input or32_d_stb_i,
>> output [31:0] or32_d_dat_o,
>>
>>
>> // Debug Master
>> input [31:0] dbg_adr_i,
>> input dbg_cyc_i,
>> input dbg_stb_i,
>> output [31:0] dbg_dat_o,
>>
>>
>> // Internal rwx RAM Memory
>> output [31:0] irwx_ram_adr_o,
>> output irwx_ram_cyc_o,
>> output irwx_ram_stb_o,
>> input [31:0] irwx_ram_dat_i,
>>
>>
>> // Internal GPIO_0
>> output [31:0] gpio_0_adr_o,
>> output gpio_0_cyc_o,
>> output gpio_0_stb_o,
>> input [15:0] gpio_0_dat_i,
>>
>>
>> output [7:0] test_vect
>>
>> );
>>
>> `define MASTER_NONE 4'b0000
>> `define MASTER_I_OR1K_i 0
>> `define MASTER_I_OR1K_d 1
>> `define MASTER_I_DBG 3
>>
>> reg [3:0] master_curr = `MASTER_NONE;
>>
>> assign test_vect[3:0] = master_curr;
>>
>>
>> // priority selector
>> always @(dbg_cyc_i or or32_i_cyc_i or or32_d_cyc_i or wb_rst) begin
>> if (wb_rst)
>> master_curr = `MASTER_NONE;
>> else begin
>> if (dbg_cyc_i) begin
>> master_curr = 4'b0001 << `MASTER_I_DBG;
>> end else if (or32_i_cyc_i) begin
>> master_curr = 4'b0001 << `MASTER_I_OR1K_i;
>> end else if (or32_d_cyc_i) begin
>> master_curr = 4'b0001 << `MASTER_I_OR1K_d;
>> end else begin
>> master_curr = `MASTER_NONE;
>> end
>> end
>> end
>>
>>
>> ///////////////////////////////////////////////////
>> // bus multiplexer
>> ///////////////////////////////////////////////////
>>
>> reg [31:0] internal_adr_ms;
>> reg internal_cyc_ms;
>> reg internal_stb_ms;
>> reg [31:0] internal_dat_sm;
>>
>>
>> // Address decoder
>> wire select_rwx_int_ram;
>> wire select_gpio;
>> wire bank0;
>> wire bank00;
>> wire bank01;
>>
>>
>> assign bank0 = (internal_adr_ms[31:24] == 8'h00) &&
>> internal_cyc_ms && internal_stb_ms;
>> assign bank00 = (internal_adr_ms[23:16] == 8'h00) && bank0;
>> assign bank01 = (internal_adr_ms[23:16] == 8'h01) && bank0;
>> assign select_rwx_int_ram = bank00;
>> assign select_gpio = bank01 && (internal_adr_ms[15:2] == 14'd0);
>>
>> always @(*)
>> begin
>> if (master_curr[`MASTER_I_OR1K_i]) begin
>> internal_adr_ms = or32_i_adr_i;
>> internal_cyc_ms = or32_i_cyc_i;
>> internal_stb_ms = or32_i_stb_i;
>> end else if (master_curr[`MASTER_I_OR1K_d]) begin
>> internal_adr_ms = or32_d_adr_i;
>> internal_cyc_ms = or32_d_cyc_i;
>> internal_stb_ms = or32_d_stb_i;
>> end else if (master_curr[`MASTER_I_DBG]) begin
>> internal_adr_ms = dbg_adr_i;
>> internal_cyc_ms = dbg_cyc_i;
>> internal_stb_ms = dbg_stb_i;
>> end else begin
>> internal_adr_ms = 32'h00000000;
>> internal_cyc_ms = 1'b0;
>> internal_stb_ms = 1'b0;
>> end
>>
>> if (select_rwx_int_ram) begin
>> internal_dat_sm = irwx_ram_dat_i;
>> end else if (select_gpio) begin
>> internal_dat_sm = gpio_0_dat_i;
>> end else begin
>> internal_dat_sm = 32'h00000000;
>> end
>>
>> end
>>
>> assign irwx_ram_adr_o = internal_adr_ms; //select_rwx_int_ram ?
>> internal_adr_ms : 32'h00000000;
>> assign irwx_ram_cyc_o = internal_cyc_ms & select_rwx_int_ram;
>> assign irwx_ram_stb_o = internal_stb_ms & select_rwx_int_ram;
>>
>> assign gpio_0_adr_o = internal_adr_ms; //select_gpio ?
>> internal_adr_ms : 32'h00000000;
>> assign gpio_0_cyc_o = internal_cyc_ms & select_gpio;
>> assign gpio_0_stb_o = internal_stb_ms & select_gpio;
>>
>> assign or32_i_dat_o = internal_dat_sm;
>> //master_curr[`MASTER_I_OR1K_i] ? internal_dat_sm : 32'h00000000;
>> assign or32_d_dat_o = internal_dat_sm;
>> //master_curr[`MASTER_I_OR1K_d] ? internal_dat_sm : 32'h00000000;
>> assign dbg_dat_o = internal_dat_sm; //master_curr[`MASTER_I_DBG]
>> ? internal_dat_sm : 32'h00000000;
>>
>>
>> endmodule //BusMatrix
>
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