Verilog a FPGA (bylo FPGA Altera a NIOS)

[Jaroslav Buchta]

Jak definovat průběhy pro gate level simulaci?

Pro RTL je nejlepsi vytvorit primo verilog soubor, v takovemto stylu?

`include "counter.v"
`timescale 1ns / 1ns

module counter_tb();
   // Declare inputs as regs and outputs as wires
   reg clock, reset, enable;
   wire [7:0] counter_out;

   // Initialize all variables
   initial begin
       clock = 1;       // initial value of clock
       reset = 0;       // initial value of reset
       enable = 0;      // initial value of enable
       #5  reset = 1;    // Assert the reset
       #10  reset = 0;   // De-assert the reset
       #10  enable = 1;  // Assert enable
       #100  enable = 0; // De-assert enable
       #500  $finish;      // Terminate simulation
  end

  // Clock generator
     always begin
         #10  clock = ~clock; // Toggle clock every 5 ticks
     end

  // Connect DUT to test bench
  counter U_counter (
   clock,
   reset,
   counter_out,
   enable
   );
endmodule
-------------------------------
nebo se pouziva jina metoda?

Nelze ovsem provest syntezu, chybove hlaseni Error (12061): Can't 
synthesize current design -- Top partition does not contain any logic

Kdyz provedu syntezu samotneho counter.v, tak to jde krasne simulovat na 
gate level urovni, ale vstupni prubehy musim pokazde naklikat - neprisel 
jsem nejak na logiku v altera modelsim
jak je jednou vytvorit a ulozit pro dalsi simulace. A vubec se to blbe 
dela, text je text...

Jaky je bezny postup?


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