VHDL - rychla otazka

[Zdenek Aster]

Ja si myslim, ze to bude hodne zavisle na prostredi.
Vysek jsem to z prikladu.
Ale mam takovy dojem, ze to je zavisle jen na XILINXu ta inicializace ;-(.

Zdenek Aster


   RAM128X1S_1_inst : RAM128X1S_1
   generic map (
      INIT => X"00000000000000000000000000000000")
   port map (
      O => O,        -- 1-bit data output
      A0 => A0,      -- Address[0] input bit
      A1 => A1,      -- Address[1] input bit
      A2 => A2,      -- Address[2] input bit
      A3 => A3,      -- Address[3] input bit
      A4 => A4,      -- Address[4] input bit
      A5 => A5,      -- Address[5] input bit
      A6 => A6,      -- Address[6] input bit
      D => D,        -- 1-bit data input
      WCLK => WCLK,  -- Write clock input
      WE => WE       -- Write enable input
   );


synopsys

   u1: asyn_rom_256x15
-- pragma translate_off
        GENERIC MAP (LPM_FILE => "u1.hex")
-- pragma translate_on
   PORT MAP (Address => addr, MemEnab => memenab, Q =>q);
END behavior;


----- Original Message ----- 
From: "Daniel Valuch" <daniel.valuch@wanadoo.fr>
To: "'HW-news'" <hw-list@list.hw.cz>
Sent: Sunday, April 30, 2006 10:27 PM
Subject: VHDL - rychla otazka


zdravim,
nemam tu so sebou svoje poznamky, preto rychla otazka... Chcem vo VHDL
nakodovat RAM, 4k x1bit co v principe nie je problem ale pre simulator
by som ju chcel mat inicializovanu, t.j. niecim naplnenu. Ako sa to
robi? Uvazujme vseobecny simulator, nie konkretne vyvojove prostredie
pre konkretny cip.
b.

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