VHDL, scitacka a CarryOut

[Hynek Sladky]

Uz zas nevim, jak dal. Potrebuju dostat signal CarryOut ze scitacky, ale 
nejak se nedari...

mam registr
   signal AddReg: std_logic_vector (7 downto 0) := "10000000";
dale vysledek
   signal CntAdd: std_logic_vector (8 downto 0);
a operace
   CntAdd <= Cnt + AddReg;
   process (Fin) begin
     if (Fin='1' and Fin'event) then
       Cnt <= CntAdd(7 downto 0);
     end if;
   end process;

Myslel jsem, ze CntAdd(8) bude obsahovat CarryOut, ale zda se, ze ne.
Preklad vyhodi Warning:
Width mismatch. <CntAdd> has a width of 9 bits but assigned expression 
is 8-bit wide.

Jak by se to dalo vyresit?

Diky,
Hynek Sladky