VHDL dotaz

[Jiri Beranek]

Ja bych to udelal asi nasledovne:

process (CS(3) ,nWR,ADDR)
begin
 if (CS(3)='1' and nWR='1' and ADDR = "00000") then
 WRD <= '1';
 else
  WRD <= '1';
 end if;
end process;

J.Ber


>Hynek Sladky wrote:
> Zacal jsem se ucit VHDL, ale nedari se mi prijit na to, jak spravne 
> napsat nasledujici rovnici (problem je zrejme s typem vysledku porovnani 
> ADDR, protoze pokud tu cast vypustim, preklad probehne OK):
>
> WRD <= CS(3) and nWR and (ADDR = "00000");
>
> kde
>
> signal WRD: std_logic;
> nWR: in std_logic;
> CS : in std_logic_vector(3 downto 0);
> ADDR : in std_logic_vector(4 downto 0);
>
> Jake reseni pouzivaji profici? :-)
>
> Diky,
> Hynek Sladky
>   


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