Třístavový buffer v CPLD

[Zdenek_Z]

Diky, ono je to nakonec docela trivialni, nasel jsem toto :

module tsbuffer
title 'bidirectional 3-state buffer'
S1,S0 Pin 1,2; Select = [S1,S0];
A3,A2,A1,A0 Pin 12,13,14,15; A = [A3,A2,A1,A0];
B3,B2,B1,B0 Pin 16,17,18,19; B = [B3,B2,B1,B0];
equations
    A = B;
    B = A;
    A.oe = (Select == 1);
    B.oe = (Select == 2);
end

tzn. stav 0 a 3 je vysoka impedance...

Zdenek

Pavel Prochazka.zde.cz wrote:

>dobry den,
>
>sice pro ABEL to nemam... mam to ve VHDL...
>
>entity transport1 is
>  Port (DIR: in std_logic;
>        A : buffer std_logic_vector(7 downto 0);
>        B : buffer std_logic_vector(7 downto 0));
>end transport1;
>
>  architecture behavioral of transport1 is
>begin
>
>   process (DIR) begin
>  -- Signál DIR určuje tok dat.
>   if DIR = '0' THEN A <= B;
>    else A <= "ZZZZZZZZ"; end if;
>
>    if DIR = '1' THEN B <= A;
>   else B <= "ZZZZZZZZ"; end if;
>
>   end process;
>end behavioral;
>
>
>P.S.: priklad je na mejch www strankach: 
>http://prochazka.d2.cz/priklady1.php#29
>
>
>Pavel Prochazka.zde.cz
>
>  
>