Xilinx, verilog - problem

[Jakub Slajs]

> Ted si nejsem jistej, ale myslim, ze jsem to tak uz zkousel. No
> protoze si to nepamatuju, jdu to zkusit znovu. jeste taky zkusim
> nahradit to if (reset==1) a pod.

No ja Vam nebudu branit ve zkouseni vsech moznych i nemoznych variant,
ale doporucuji precist si nasledujici vynatek:

"Sequential circuit description is based on always blocks with a sensitivity list.
The sensitivity list contains a maximum of three edge-triggered events:
the clock signal event (which is mandatory) and possibly a reset signal event
and a set signal event. One and only one "if-else" statement is accepted in such
an always block. An ASYNCHRONOUS part may appear BEFORE the synchronous part in
the first and the second branch of the "if-else" statement. Signals assigned
in the asynchronous part must be assigned to the constant values ’0’, ’1’, ’X’
or ’Z’ or any vector composed of these values."

Je to z "Xilinx Synthesis Technology (XST) User Guide" a myslim, ze uz jednou
jsem Vam toto PDF doporucoval k nahlednuti ;-)

S pozdravem,

Jakub Slajs
____________________________________________________________
Obchodní dům.cz - široký sortiment domácích spotřebičů a elektroniky, výrazné slevy. Navštivte 
http://ad.seznam.cz/clickthru?spotId=73742