Dalsi 8-pinovy jednocip

Pavel Poucha papouch@papouch.com
Úterý Srpen 10 15:59:26 CEST 2004


Take mi dneska prisel od Spoerle... :-) Konecne 8 noh s UARTEM.

S pozdravem
Pavel Poucha

Máte-li chuť, navštivte naše stránky http://www.papouch.com/

----- Original Message ----- 
From: "Daniel Valuch" <daniel.valuch@wanadoo.fr>
To: "[HWnews]" <hw-list@mailman.nethouse.cz>
Sent: Tuesday, August 10, 2004 3:35 PM
Subject: Dalsi 8-pinovy jednocip


> kolko tato hracka stoji? Vyzera to celkom zaujimavo...
>
> http://www.semiconductors.philips.com/cgi-bin/pldb/pip/p89lpc904fd.html
>
> Principal features
>
> * 1 kB byte-erasable Flash code memory organized into 256-byte sectors
> and 16-byte pages. Single-byte erasing allows any byte(s) to be used as
> non-volatile data storage.
> * 128-byte RAM data memory.
> * Two 16-bit counter/timers.
> * 23-bit system timer that can also be used as a Real-Time clock.
> * 2 -input multiplexed A/D converter/single DAC output. Two analog
> comparators with selectable reference.
> * Enhanced UART with fractional baud rate generator, break detect,
> framing error detection, automatic address detection and versatile
> interrupt capabilities.
> * High-accuracy internal RC oscillator option allows operation without
> external oscillator components. The RC oscillator option is selectable
> and fine tunable.
> * 2.4 V to 3.6 V VDD operating range with 5 V tolerant I/O pins (may be
> pulled up or driven to 5.5 V). Industry-standard pinout with VDD , VSS ,
> and reset at locations 1, 8, and 4.
> * Up to six I/O pins when using internal oscillator and reset options.
> * 8-pin SO-8 package.
>
> Additional features
>
> * A high performance 80C51 CPU provides instruction cycle times of 167
> ns to 333 ns for all instructions except multiply and divide when
> executing at 12 MHz. This is six times the performance of the standard
> 80C51 running at the same clock frequency. A lower clock frequency for
> the same performance results in power savings and reduced EMI.
> * In-Application Programming (IAP-Lite) and byte erase allows code
> memory to be used for non-volatile data storage.
> * Serial Flash In-Circuit Programming (ICP) allows simple production
> coding with commercial EPROM programmers. Flash security bits prevent
> reading of sensitive application programs.
> * Watchdog timer with separate on-chip oscillator, requiring no external
> components. The Watchdog prescaler is selectable from 8 values.
> * Low voltage reset (Brownout detect) allows a graceful system shutdown
> when power fails. May optionally be configured as an interrupt.
> * Idle and two different Power-down reduced power modes. Improved
> wake-up from Power-down mode (a low interrupt input starts execution).
> Typical Power-down current is 1 uA (total Power-down with voltage
> comparators disabled).
> * Active-LOW reset. On-chip power-on reset allows operation without
> external reset components. A reset counter and reset glitch suppression
> circuitry prevent spurious and incomplete resets. A software reset
> function is also available.
> * Programmable port output configuration options: quasi-bidirectional,
> open drain, push-pull, input-only.
> * Port ‘input pattern match’ detect. Port 0 may generate an interrupt
> when the value of the pins match or do not match a programmable pattern.
> * LED drive capability (20 mA) on all port pins. A maximum limit is
> specified for the entire chip.
> * Controlled slew rate port outputs to reduce EMI. Outputs have
> approximately 10 ns minimum ramp times.
> * Only power and ground connections are required to operate the
> P89LPC904 when internal reset option is selected.
> * Four interrupt priority levels.
> * One keypad interrupt input.
> * Second data pointer.
> * External clock input.
> * Schmitt trigger port inputs.
> * Emulation support.
>
>


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